The present invention relates to a semiconductor integrated circuit device formed by mainly integrating MISFETs (Metal Insulator Semiconductor Field Effect Transistor) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistor), and to a technology that is effective when applied to a technology for forming an insulating film, in particular, to a technology for forming a pre-metal interlayer insulating film, in a method of manufacturing the semiconductor integrated circuit device (or a semiconductor device).
Japanese patent laid-open No. 5-21620 discloses a technology in which a SOG (Spin-On-Glass) silicon oxide film is coated over a TEOS (Tetra-Ethyl-Ortho-Silicate)-CVD (Chemical Vapor Deposition) silicon oxide film using TEOS to be planarized and these are etched back by dry etching, as a technology for forming a pre-metal interlayer insulating film.
Japanese patent laid-open No. 5-206474 discloses a technology in which a TEOS-CVD silicon oxide film using TEOS is reflowed for planarization and then etched back.
Japanese patent laid-open No. 2002-110666 discloses a technology in which a CVD silicon oxide film by P-TEOS (Plasma-TEOS) is formed over a CVD silicon oxide film by HDP (High Density Plasma), and the CVD silicon oxide film by P-TEOS is subjected to CMP (Chemical Mechanical Polishing) or to etching back for planarization, and then, a CVD silicon oxide film by P-TEOS is formed as a cap film.
Japanese patent laid-open No. 2000-208624 discloses, as a technology for forming a pre-metal interlayer insulating film, a technology for forming a silicon oxide film by a plasma CVD method using O3-TEOS, then, polishing the silicon oxide film by a CMP method until the conductive layer of the gate electrode is exposed, and further forming a silicon oxide film on it by a CVD method using PH3—SiH4—O2.
Japanese patent laid-open Nos. 7-147281 and 3-194932 disclose a technology for forming a silicon oxide film between wirings by CVD using O3-TEOS, then removing the silicon oxide film by etching back or CMP until the upper portion of the wiring is exposed, and further forming a silicon oxide film on it by plasma CVD using TEOS.
Japanese patent laid-open No. 7-221179 discloses a technology for filling an area between wirings with an O3-TEOS NSG silicon film (which generates in-situ reflow at the deposition), then forming a silicon oxide film by plasma CVD, and then planarizing it by CMP.